1. Field of the Invention
The present invention is related to methods for testing micro-electronic devices, such as CMOS devices, by monitoring the ‘quiescent current’ IDDQ, for a set of test vectors applied to the device under test.
2. Prior Art
IDDQ monitoring is a widely applied technique for fault detection in micro-electronic devices. A device-under-test (DUT) is subjected to a predefined series of test vectors, which are basically digital inputs, applied to the DUT at every pulse of the operational clock frequency. The DUT receives a supply current, generated by a supply voltage VDUT. The switching action of the DUT, in most cases related to an ‘active’ (rising or falling) edge of the clock signal, is accompanied by a sharp peak in the supply current, which can reach levels in the order of amps or higher. After such a peak, the current returns to a low level (typically not more than 10 mA), called the ‘quiescent current’ IDDQ. This level is representative of the quality of components on the DUT. IDDQ levels must remain within narrow limits for given DUT operating conditions (temperature, voltage): in particular a sharp (vector related) rise of the IDDQ is indicative of component failures.
Existing IDDQ monitors are based on this basic principle: these monitors measure the IDDQ level, compare it to a predefined level, and deliver a pass/fail signal, indicating whether the DUT is operating properly or not. Most monitors allow additional features, such as the output of the IDDQ value, the measurement of current signatures, or the assessment of delta-IDDQ values. This means that subsequent IDDQ values are subtracted, and compared to a reference value for this delta value.
A problem with these standard techniques, in particular the fixed reference, is that IDDQ levels can vary from one device to the other, even between devices of the same type. This makes it difficult to define a fixed reference level for a given device type: it may be possible that for some individual devices, the reference is closely approached or even exceeded by the measured IDDQ levels, even though no error occurs on the tested device. The same goes for delta IDDQ values, which may be higher for a device which has, on average, a higher IDDQ level, than for a device of the same type, with a lower average IDDQ. A solution to overcome the above mentioned problems could be to widen the acceptance criteria. However, this approach has the disadvantage of losing device screening efficiency with as a result that bad parts may not be properly identified as such.
Modern Integrated Circuits are heading into the deep-submicron area in terms of component size. This is leading to an increase in background leakage current. The result is that the IDDQ is composed of this large, non-defect-related background current, and a small defect-related current. For deep submicron IC technologies, the current caused by an IC defect (short, bridging fault, open, gate oxide leakage, . . . ) in many cases could become very small, e.g. below 1 μA. On the other hand, when comparing one IC to the other, the variation in off state current of the different transistors on the IC, is large.
These variations in off state leakage current, are due to process fluctuations, which affect to a large extent all transistors on the IC. Examples are gate length definition, doping concentration under the gate, . . . For a deep submicron IC process (e.g. 0.13 um CMOS), used to fabricate an IC with a large number of transistors (1 million of transistors or more), the variation in IC off state leakage current can be orders of magnitude larger than the leakage current caused by a single IC defect. This makes it impossible for deep submicron circuits to use absolute leakage current levels, in order to separate “good IC's” from “IC's with a defect”.
The most relevant prior art can be found in:    Y. Okuda, Eigen Signatures for Regularity-Based IDDQ testing, Proceedings of the VLSI Test Symposium 2002, pp 289-294 (ISBN 0-7695-1570-3)    P. Maxwell et al, Current Ratios: A Self-Scaling Technique for Production IDDQ Testing, Proceedings of the International Test Conference ITC'99, paper 28.4, pp 738-746    B. Kruseman et al, The Future of Delta-IDDQ Testing, Proceedings of the International Test Conference ITC'2001, pp 101-110